Efficient VLSI fault simulation

Efficient VLSI Fault Simulation

Distributed Fault Simulation with Collaborative Load Balancing for VLSI Circuits

In this paper we present a web-based distributed fault simulation framework built with standard Java Applet/Servlet technology and the popular platform independent open source database MySQL. Fault simulation plays an important role in digital electronics design flow by creating and evaluating test patterns, identifying and locating the causes of the circuit failures. Because of the rapid incre...

Efficient Single-Pattern Fault Simulation on Structurally Synthesized BDDs

Current paper proposes an efficient alternative for traditional gatelevel fault simulation. The authors explain how Structurally Synthesized Binary Decision Diagrams (SSBDD) can be used for representation, simulation and fault modeling of digital circuits. It is shown how the first phase of any fault simulation algorithm: the fault-free simulation can be accelerated using this model. Moreover, ...

Efficient Concurrent Simulation of Large Networks Using Various Fault Models

An improved fault simulation environment is described in this paper, and details of its faulting capability are presented and tested. The versatility of our fault simulator in handling different fault models by adding new activity functions to our modeling structure such as n-terminal bridge faults is shown. We use our TUFTsim simulator, which is based on concurrent simulation algorithms to eff...

Support for Fault Tolerance in Vlsi Processors †

Fault tolerance techniques are used to allow computer systems to continue correct operation despite component failure. Hardware-supported concurrent error-detection and limited fault tolerance in system components, as implemented by coding or replication, are often required. Detection latency can be reduced by increasing the visibility of internal module state using compressed ‘‘signatures’’ of...